Memory controllers frequently are utilized in processing systems to control access to memory resources for devices seeking to store data to memory or access data from memory. In conventional systems, memory access requests are supplied to a memory controller based on certain fixed priorities. However, the selection for memory access requests based solely on a fixed prioritization scheme often can introduce significant penalties in page-based memories, such as dynamic random access memories (DRAM). Typically, a delay is introduced whenever a different page of a DRAM is accessed due to the process required to close the previous page and open the next page. Frequent switching between pages of memory, as typically occurs in a fixed prioritization scheme, therefore often results in “thrashing” in the memory and, consequently, introduces a significant cumulative delay in memory access request sequences. This problem is especially pronounced in dual data rate (DDR) memories due to their higher data rates per command cycle.
Accordingly, an improved technique for processing memory access requests would be advantageous.